1. Field of the Invention
The present invention relates to semiconductor integrated circuits and, more particularly, to a high speed ECL programmable array logic device which utilizes a unique voltage reference circuit for the program driver and a new ECL output disable control circuit to allow for TTL programming.
2. Discussion of the Prior Art
Programmable logic devices are essentially uncommitted logic gates where the user determines the final logic configuration of the device. The internal structure of these devices is a fuse-programmable interconnection of AND gates, OR gates and registers which allows the user to design combinational as well as sequential circuits.
The first programmable logic device was the diode matrix, which was introduced in the early 1960's. This device featured rows and columns of metalization connected at the cross points with diodes and aluminum fuses. These fuses could be selectively melted, leaving some of the cross points open and others connected. The result was a diode-logic OR matrix.
Input decoders and output buffers were then added to the basic diode matrix, creating the field-programmable read-only memory (PROM). The PROM extended the programmable-logic concept considerably, since the input variables could now be encoded. It also reduced the number of pins required per input variable. At the same time, the input circuitry, along with the output buffers, provided TTL compatibility, the lack of which was one of the drawbacks of the diode matrix. A decoder is nothing more than a collection of AND gates that combine all the inputs to produce product terms. The basic logic implemented by the PROM is AND-OR with the AND gates all preconnected on the chip, making this portion fixed. The OR matrix is implemented with diode-fuse interconnections, making it programmable. Thus, the PROM is an AND-OR logic device with a fixed AND matrix and a programmable OR matrix.
However, it is difficult to accommodate a large number of variables with PROMs. For each variable added to the PROM, not only does the package size increase by one pin, but the size of the matrix doubles as well. Therefore, as a practical matter, PROMs are limited in the maximum number of input variables they can be designed to handle.
The field-programmable logic array (FPLA) overcomes some of the size restrictions of PROMs. By utilizing a second fuse matrix, an AND matrix, the FPLA allows the designer to select and program only those product terms used in each specific function. These product terms are then combined in the OR fuse array to form an AND-OR logic equation. An ECL FPLA is described by Schmitz et al., "An ECL Field Programmable Logic Array", 1984 IEEE International Solid-State Circuits Conference, p. 264. However, because of the dual fuse matrix and the overhead cost of the circuitry required for programming, the FPLA cannot be used economically in low complexity logic applications.
Cost savings similar to those of PROMS can be made without the penalty of restricting the input variables, by removing the OR matrix from the FPLA, or hard wiring it. Thus, in the programmable array logic device concept, the AND fuse array allows the designer to specify the product terms required. The terms are then hard wired to a predefined OR matrix to form AND-OR logic functions.
Because the OR gates in a programmable array logic device are prewired, the degree to which the product terms can be combined at these OR gates is restricted. Programmable array logic vendors partially compensate for this by offering different part types with varying OR-gate configurations. Specifying the OR-gate connection, therefore, becomes a task of device selection rather than one of programming, as with the FPLA. With this approach, programmable array logic devices eliminate the need for a second fuse matrix with little loss in overall flexibility.
Recently, programmable array logic devices have been implemented in emitter-coupled logic technology (see Millhollan and Sung, "A 3.6 ns ECL Programmable Array Logic IC", 1985 IEEE International Solid-State Circuits Conference, p. 202). Emitter-coupled logic (ECL) is best known for its high-speed operation. ECL is a non-saturating form of digital logic that eliminates transistor storage time as a speed-limiting characteristic, permitting very high speed operation.